1. Field of the Invention
Embodiments of the present invention relate to an output driver with reduced coupling noise.
This application claims the priority of Korean Patent Application No. 2003-47540, filed on Jul. 12, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
A current-mode output driver may have a relatively high output resistance when it is turned on or off. Accordingly, a current-mode output driver is beneficial for channel impedance matching. A current-mode output driver may be necessary in some types of Rambus dynamic random access memory (Rambus DRAM) and is commonly used in chip-to-chip connection systems.
FIG. 1 illustrates a current-mode output driver 100, which includes a NMOS transistor NTR connected between a channel and a ground voltage VSS. A voltage level at a gate of the NMOS transistor NTR is based on a logic level of data DATA. A drain current Id is generated according to the voltage level at the gate of this NMOS transistor NTR. The drain current Id flows through the channel or a conducting wire. However, when the current-mode output driver 100 is turned on (when the drain current Id flows), the output resistance must be high. As a result, the NMOS transistor NTR of the current-mode output driver 100 must be operating in saturation when the current-mode output driver is turned on.
In order for the NMOS transistor NTR of the current-mode output driver 100 to operate in saturation, the voltage level at the gate of the NMOS transistor NTR must be less than a voltage level at a drain of the NMOS transistor NTR. The voltage level at the drain of the NMOS transistor NTR is equal to the sum of a turn-on voltage level of the channel and a threshold voltage of the NMOS transistor NTR. Accordingly, if the data DATA, having a supply voltage level, is applied to the gate of the NMOS transistor NTR, then a low voltage is generated at the drain of the NMOS transistor NTR (in the channel). Accordingly, the condition that the voltage at the gate should be less than the voltage at the drain will not be satisfied, resulting in a low output resistance of the current-mode output driver 100.
Consequently, when an output driver includes only a single MOS transistor, as shown in FIG. 1, a gate of the MOS transistor can not be charged to a ground voltage level or the supply voltage level, according to the level of data applied to the gate of the MOS transistor. Instead, the gate of the MOS transistor must be charged to the ground voltage level or a specific voltage level VA. The specific voltage level VA is between the threshold voltage of the MOS transistor and the supply voltage. However, the new voltage level VA, requiring a large amount of current, must be internally generated, there may be disadvantageous chip size and power consumption consequences.
FIG. 2 illustrates a stacked current-mode output driver 200. The stacked current-mode output driver 200 includes first NMOS transistor NTR1 and second NMOS transistor NTR2 that are connected serially between a channel and a ground voltage VSS. A gate voltage ENVG, maintained at a specific level, is applied to a gate of the second transistor NRT2 connected to the channel. Data DATA that swings between a supply voltage VDD and the ground voltage VSS is applied to a gate of the first transistor NTR1.
Once the gate voltage ENVG is applied to the gate of the second transistor NTR2, the second transistor NTR2 is maintained in a saturation state and an output resistance of the stacked current-mode output driver 200 is maintained at a high level. Since the gate voltage ENVG applied to the gate of the second transistor NTR2 is maintained at a specific level, irrespective of changes in the data DATA, the amount of supplied current does not need to be large. Thus, the structure of the stacked current-mode output driver 200 of FIG. 2 is advantageous for generating and controlling accurate voltages.
In a Rambus DRAM, the gate voltage ENVG may be lowered to the ground voltage VSS in a stand-by state and increased to a voltage Vgate in an active-read state, making the stacked current-mode output driver 200 available. Since the data DATA applied to the gate of the first transistor NTR1 swings between the ground voltage VSS and the supply voltage VDD, driving current of the stacked current-mode output driver 200 is determined by the voltage Vgate. In other words, the driving current of the stacked current-mode output driver 200 is effected by the change in the voltage Vgate, which may have an influence upon the amplitude and timing of signals on the channel.
Coupling noise introduced at the gate of the second transistor NTR2 exerts a negative influence on the characteristics of signals on the channel. To minimize such coupling noise, a large-capacitance capacitor may be included between the gate of the second transistor NTR2 and the ground voltage VSS.
FIG. 3 illustrates coupling noise generated in the stacked current-mode output driver 200 of FIG. 2. Referring to FIG. 3, when the level of the data DATA is 1 or 0, a drain node of the second transistor NTR2 (e.g. the channel) may experience a voltage swing of about 800 mV. Also, a first node N1 between the first transistor NTR1 and the second transistor NTR2 may experience a voltage swing of about 500 mV. These voltage swings may vary with the design of the output driver. In other words, when a voltage at the gate of the first transistor NTR1 increases to the supply voltage VDD, the channel undergoes a voltage drop of 800 mV and the first node N1 undergoes a voltage drop of 500 mV. Such changes in the voltages of the channel and the first node N1 effect the voltage at a gate node GNODE of the second transistor NTR2 through parasitic capacitances Cgd and Cgs of the second transistor NTR2. The amount of change in voltage at the gate node GNODE of the second transistor NTR2 (i.e. a coupling voltage Vcoup) may be approximated by the following equation.Vcoup=(800 mV*Cgd+500 mV*Cgs)/(C+Cgd+Cgs)  (1)
The number of transmission paths of the coupling voltage Vcoup defined in Equation 1 is two. That is, one transmission path is the channel that experiences the voltage swing of 800 mV and the other transmission path is the first node N1 that experiences the voltage swing of 500 mV. The amount of coupling noise is proportional to the product of the amount of voltage change at nodes by the mutual capacitances Cgd and Cgs. Since Cgs is generally larger than Cgd, most of the coupling noise is introduced by the first node N1.
As can be seen from Equation 1, when a capacitor C, with a capacitance much larger than the mutual capacitances Cgd and Cgs, is connected between the gate node GNODE of the second transistor NTR2 and the ground voltage VSS, it is possible to minimize the coupling voltage Vcoup. However, since sizes of the first transistor NTR1 and the second transistor NTR2 of an output driver 300 of FIG. 3 may be relatively large, the parasitic capacitances Cgd and Cgs may also be relatively large. Accordingly, there are limitations on the layout of the capacitor C between the gate node GNODE of the second transistor NTR2 and the ground voltage VSS, because the capacitance of the capacitor C should be larger than Cgd and Cgs.
The large-capacitance capacitor C also interferes with charging and discharging of the gate node GNODE of the second transistor NTR2 to a level of Vgate or Vss. Accordingly, in a Rambus DRAM, a coupling voltage Vcoup of tens of mV is generated at the gate node GNODE of the second transistor NTR2. In the Rambus DRAM, the gate node GNODE of the second transistor NTR2 may be shared with 8 output drivers (not shown). As a result, when all of the output drivers are pulled down, the coupling voltage Vcoup at the gate node GNODE of the second transistor NTR2 decreases, and as a result, output time tQ of the data DATA is delayed. In contrast, when one output driver is pulled down and the other 7 output drivers are pulled up, the coupling voltage Vcoup at the gate node GNODE of the second transistor NTR2 increases. As a result, the output time tQ of the data DATA moves forward in time. In other words, the coupling noise changes the output time tQ of the data DATA, thus interfering with high-speed signal transmission between chips.